VHDL 1 for Engineers

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VHDL 1 for Engineers

MQF Level 5; 6 ECTS


 Course Rationale


VHDL is a hardware descriptive language used worldwide for the design and implementation of electronic systems at component and board level. This couse is aimed to introduce the learner to the modern digital design environments and to build the basic skills in getting familiar with the VHDL concepts, FPGA, EDA tools and boards. The concepts presented in the lectures are accompanied with guided hands-on practical training.


 


Learning Outcomes

LO 1. Explain FPGA architecture, features and programmable link hardware.

LO 2. Apply VHDL basic concepts to describe a system hierarchically.

LO 3. Efficiently simulate VHDL models.

LO 4. Use FPGA design tools to create a combinational and sequential hardware circuits 

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